Tendy The

Tendy The is an experienced RTL/IP/Logic/SoC designer with over 12 years of expertise in RTL design using Verilog/SystemVerilog and various design tools. Currently a Principal Engineer at Arm, Tendy has previously held key roles at notable companies including AMD, Motorola, and Freescale Semiconductor. Tendy's strong background encompasses micro-architecture development, Ethernet controller design, and extensive experience in IP verification and synthesis. Currently pursuing a Master of Engineering at the University of Auckland, Tendy continues to enhance their skills in the engineering field.