utkarsh vij

Utkarsh Vij is a Staff Physical Design/STA Engineer at Arm, bringing over nine years of experience in physical design and static timing analysis. Previously, Utkarsh served as a Principal Application Engineer at Cadence and a Senior Lead Engineer at Qualcomm, contributing to more than 15 successful tapeouts of premium tier chips across advanced technology nodes. Utkarsh has expertise in timing closure for complex designs with over 40 million gates, establishing STA flows, and leading diverse teams across geographies. They hold a Bachelor’s Degree in Electronics and Communications Engineering from Motilal Nehru National Institute Of Technology.