Vinay Vedula

Vinay Vedula is a design verification engineer with extensive experience in leading verification planning and execution, developing verification environments, and conducting functional coverage analysis. They have held positions as a Senior Manager at Tenstorrent Inc. and as a Principal Engineer at Arm, where they also served as a Staff Verification Engineer and Senior Verification Engineer previously. Vinay has a strong expertise in System Verilog, Verilog HDL, and various verification methodologies, and has hands-on knowledge of post silicon validation. Their education includes a degree obtained between 1999 and 2003.