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Christophe C.

Senior Staff Software Engineer at Arteris

Christophe C. has a diverse work experience spanning several companies. Christophe is currently employed at Arteris as a Senior Staff Software Engineer, a position they have held since April 2022. Prior to this role, they worked as a Senior Software Engineer at Arteris from December 2020 to April 2022.

Christophe also worked at Magillem as a Software Development Engineer from September 2017 to December 2020.

Before Magillem, they were a Software Development Engineer at NAGRA, where they focused on back-end and front-end software development for DVB, IPTV, and OTT based pay TV Conditional Access Systems. Working as part of the Head-End agile team, they were responsible for conception, development, tests, and support of digital rights management. Christophe collaborated with multiple teams across Europe and India during their tenure at NAGRA, which lasted from April 2004 to August 2017.

Prior to NAGRA, Christophe worked as a Software Development Engineer at CANAL+ from January 2001 to April 2004. Here, they were a member of the transversal database expertise team, providing solutions and Oracle DB APIs to the Mediaguard teams. Christophe utilized programming languages such as Ada, C, C++, and Oracle PL/SQL, and worked with technologies such as VAX/VMS, UML, Merise, Synergy, SVN, and CVS.

At the start of their career, Christophe worked at Gfi Informatique as a Software Development Engineer. Christophe developed on-site projects for public institutions and private companies, including BNP-Paribas and CCPBRP (pension fund of the construction industry). Their work involved financial products compliance management and controllers management, amongst other tasks. Christophe utilized PowerBuilder and Oracle, and worked on Windows 95/XP. Their tenure at Gfi Informatique lasted from 1995 to 2000.

Before Gfi Informatique, Christophe worked at ST Groupe as a Software Development Engineer from January 1992 to 1995. Here, they worked on in-house and on-site projects for various institutions and companies, including EDF, CEA, DGA, and ANPE. Christophe utilized ObjectView, Clipper, and Progress, and worked on Windows 3. 1.

Christophe C. started their education in 1988 at IUT de Sceaux, where they pursued a DUT degree in Gestion des PME. Christophe completed their studies there in 1990. The following year, from 1990 to 1991, Christophe attended IUT d'Orsay, where they earned another DUT degree in Informatique. In 2016, they enrolled in ORSYS for professional training in Javascript and AngularJS. The end year for this training is not specified.

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Arteris

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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.


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