Maxime Joubert

Maxime Joubert is a hardware engineer with extensive experience in digital design and FPGA development, currently working at Arteris since November 2023. Prior to this role, Maxime served as a Digital Design Engineer at SCALINX from April 2021 to October 2023 and as a SoC/IP Engineer at Nokia from March 2018 to November 2020, where responsibilities included 5G algorithm architecture study, HLS and RTL implementation, and performance verification. Earlier experience includes FPGA engineering roles at Elsys Design, focusing on safety-critical FPGAs and video processing applications. Maxime holds a degree from ESIEE Paris and has also studied at Brno University of Technology.