Arteris
Sharon Vu has a diverse work experience spanning over 25 years. Sharon is currently working at Arteris IP as a Senior Manager in Treasury & Analytics, a role they started in October 2021. Prior to that, they worked as a Senior Accounting Manager at Arteris IP from March 2020 to October 2021.
Before joining Arteris IP, Sharon worked at Corsair as a Senior Accountant from June 2018 to March 2020. Prior to that, they worked at the City of San José as a Senior Accountant from October 2014 to June 2018.
From 2010 to 2014, Sharon worked at Trident Microsystems as a Corporate Staff Accountant. Sharon'sresponsibilities included managing worldwide cash and investments accounts, funding subsidiaries, preparing financial reports, reconciling accounts, and supporting SOX key controls.
Prior to their time at Trident Microsystems, Sharon worked at VICIS Corp as a Senior Accountant from January 2006 to January 2010, where they managed AP activities, handled General Ledger accounts, and filed tax reports.
Sharon also has experience working as a Contractor at Fremont Bank in 2010 and as an Accounting Manager at Valiant Networks Inc. from 2000 to 2004, where they managed staff, resolved issues, and handled AP activities.
Earlier in their career, Sharon worked at Plextor Corp. as an Accountant from July 1998 to December 1999, where they generated reports, reconciled accounts, and addressed customer issues. Sharon also worked at Itochu Corp. as an Accountant from January 1996 to July 1998, where they processed invoices, audited expenses, and generated vendor checks.
Sharon Vu attended San Jose State University from 1991 to 1995, where they pursued a Bachelor's degree in Accounting and Finance.
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Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.