Andre Mansano was born in Jaboticabal, Brazil, in 1982. They received a BEng from Universidade Estadual Paulista in 2006 and an M.Sc. from Universidade Estadual de Campinas in 2009. They began their career at Freescale Semiconductor in 2007 as an analog mixed-signal designer, where they developed various analog IPs and contributed to multiple patents and publications. Currently, they serve as a Mixed Signal Design Architect at ASML since 2021 and are pursuing a Ph.D. at Delft University of Technology, focusing on research related to wireless energy harvesting and low-power communication technologies.
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