Bart Vorstermans is a PLC Software Designer at ASML since March 2025, bringing extensive experience from previous roles at Vanderlande where Bart held multiple positions including R&D Controls Development Engineer, Specialist R&D Development Engineer, Senior R&D Controls Engineer, and R&D Product Architect from January 2014 to January 2016. Prior experience also includes working as a Student Controls Engineer and Controls Designer at VerAutomation B.V. from 2005 to December 2007, as well as serving as a Controls Designer at ICT Group from January 2012 to December 2013. Bart holds a Bachelor's degree in Electrical Engineering Technologies/Technicians, having studied at Rythovius College, ROC Eindhoven, and Avans Hogeschool.
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