Chia-Hsien Yao is a Principal Applications Scientist at ASML, currently focusing on customer technology roadmaps and process development in CFET while scaling 2D transistor development. With over 10 years of experience in advanced logic technology development, Chia-Hsien previously served as a Principal Process Integration Engineer at TSMC and 台灣積體電路製造股份有限公司, where they contributed to process development for 20nm, 10nm, 5nm, and 2nm technologies, including yield ramp-ups and product qualifications. Chia-Hsien holds a PhD in Materials Science and Engineering from National Tsing Hua University.
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