Jasper Siemons is a Group Team Leader and Release Train Engineer at ASML, where they currently lead projects involving systems engineering and digital signal processing. With a robust background in FPGA/ASIC design, simulations, and wireless communication standards, Jasper previously served as a Senior Expert in Systems & Simulations at IMST GmbH for over two decades. Their academic foundation includes a Master’s degree in Telecommunications from Eindhoven University of Technology. Jasper's programming skills encompass languages such as Matlab, Python, VHDL, and C++.
Location
Eindhoven, Netherlands
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