Jeff Zhang

Jeff Zhang is a Senior FPGA Engineer at ASML since April 2022, bringing extensive experience from prior roles including Principal Electrical Engineer and Team Lead at Halliburton from 2012 to May 2022, where responsibilities included Logging While Drilling (LWD) and Measurement While Drilling (MWD) as well as the GeoTap Fluid Identification and Sampling Sensor (IDS) project. Previously, Jeff held the position of Senior Electrical Engineer at Baker Hughes between 2008 and 2012, contributing to the Intelligent Well System (IWS). Jeff's career began as an ASIC Design Engineer II at Fujitsu Network Communications in 2008. Academic qualifications include degrees from The University of Texas at Dallas, Wright State University, and Zhejiang University.