Jianfeng Zhang

Jianfeng Zhang is an experienced ASIC/FPGA Design Engineer currently serving as a Senior FPGA Design Engineer II at ASML, a position held since 2024. With a strong background in the semiconductors industry, Jianfeng possesses skills in FPGA design and verification, including RTL Verilog/VHDL, PCIe, and various protocols. Prior to this role, Jianfeng worked as a Graduate Teaching Assistant at NYU Tandon School of Engineering and completed an internship in process integration at Texas Instruments. Jianfeng earned a Bachelor's Degree in Electrical and Electronics Engineering from the University of Electronic Science and Technology and a Master's Degree in Computer Engineering from New York University.