Peter de Veen

Peter de Veen is a Senior System Industrialization Engineer at ASML, where they utilize their expertise in failure analysis and reliability within display and semiconductor technology. With a PhD in Science and Technology from the University of Twente, Peter has held various roles including Quality & Reliability Architect and Senior Quality & Reliability Engineer at ASML, focusing on root cause analysis and cross-sector process improvements. Prior to ASML, Peter was an R&D Manager at MASER Engineering, where they led EU and NL research projects and managed a department dedicated to physical analysis. Their extensive background is complemented by a strong commitment to improving product quality and fostering collaboration across teams.