Pieter Heres is a senior design engineer and domain architect at ASML, with extensive experience in the Metrology software department. They have cultivated expertise in alignment software, wafer positioning, deformation measurements, and overlay improvements. Previously, Pieter held various roles at ASML, including domain architect for wafer alignment and project integration lead, focusing on the technical aspects of Metrology software projects. Pieter earned a PhD in Applied Mathematics from Technische Universiteit Eindhoven, where they researched model order reduction on passive networks, and they also hold a Master's degree in the same field. Outside of work, Pieter enjoys reading, cycling, and running.
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