俊偉 黃 is an experienced EUV UIR project lead with a solid background in lithography and system installation. They served as a Quality Engineer at ADATA Technology from 2011 to 2013, where they focused on new product introduction and quality improvement. From 2013 to 2017, they worked as a Process Engineer at STATS ChipPAC, specializing in WLCSP processes. Subsequently, at 艾司摩爾, they held multiple roles, including DUV System Installation Engineer and EUV CSE, before advancing to their current position leading EUV UIR projects. 俊偉 earned a Bachelor's degree in Industrial Engineering from Yuan-Ze University in 2010.
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