Valerio Altini is a System Engineer and Architect currently working at ASML as a Senior Architect, focusing on performance-quality-cost balanced system specifications for DUV lithography. They previously served in various roles at ASML, including Design Engineer and Functional Architect in the Metrology group, where they contributed to the development and integration of lithographic systems. Valerio holds a PhD in Particle Physics from the Università degli Studi di Bari and has experience as a Detector Physicist at CERN, where they were involved in the Silicon Pixel Detector for the LHC Run I.
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