Alexandre Gicquel is an experienced digital engineer currently working at Assystem since February 2022, where responsibilities include leading the migration project of Planisware from version V6 to E7, highlighting strong project management and software expertise. Previously, Alexandre completed a research associate internship at Alma Mater Studiorum - University of Bologna during summer 2021, focusing on developing advanced features in the open-source software System Lab Design for telecommunications simulations. Educational qualifications include a Brevet de technicien supérieur in Système Numérique from Jacquard (2015-2017), an engineering degree in Systèmes Électroniques Intelligents from ESIEE Paris (2018-2022), and a Baccalauréat Technologique in Systèmes d'Information et Numérique from Lycée Clement Ader (2013-2015).
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