Soh Serine

Soh Serine has extensive experience in the semiconductor industry, with a career spanning over 25 years and a focus on packaging development, process engineering, and new material evaluation. Currently, Soh Serine works at the Institute of Microelectronics as a specialist in Fan-Out Wafer Level Packaging since September 2013. Previous roles include R&D Engineer at NEPES PTE LTD, where responsibilities encompassed new material evaluations, technology process development, and cost reduction projects. Soh Serine also worked as a Process Engineer at STATS ChipPAC and Advanpack Solutions Pte Ltd, managing projects in copper plating, solder deposition, and photolithography while collaborating with various institutes and vendors. Beginning as an Engineering Assistant at AMD, Soh Serine contributed to product development and quality engineering efforts, maintaining cross-functional alignment during new product qualifications. Notable accomplishments include holding a semiconductor packaging method patent published in 2013.