Ya-Ching Tseng

Ya-Ching Tseng is a seasoned professional in semiconductor advanced packaging, currently serving as a Senior Research Engineer at the Institute of Microelectronics since February 2022, focusing on 2.5D/3D chip and wafer packaging technologies. Prior experience includes two pivotal roles as a Senior Process Engineer at REC, where Ya-Ching led projects on Heterojunction Technology for solar cells, and as a Senior R&D 3DIC Integration Engineer at TSMC, where Ya-Ching formulated advanced packaging processes for energy-efficient chips. Earlier work at TSMC also included responsibilities as a Junior R&D 3DIC Integration Engineer. Ya-Ching holds a Master of Science in Mechanical Engineering from Penn State University, an MBA from National Taiwan University, and a Bachelor's degree in Mechanical Engineering from National Tsing Hua University.