Amit Rane is a distinguished engineer currently working at Astera Labs since April 2025, bringing extensive experience in IC design and management. Previously, Rane served as an Analog IC Design Manager at Texas Instruments from January 2007 to April 2025, leading the design of high-speed serial links and a variety of high-performance analog circuits. Rane's early career at Intel from 1998 to 2007 as a Design Manager focused on Pentium CPU design, contributing expertise in CMOS analog and digital circuits. Rane holds a Master of Science in Electrical Engineering from UCLA, awarded in 2011.
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