Aneeshkumar Polineni is a formal verification engineer with extensive experience in the semiconductor industry. Starting a career at Cadence Design Systems in early 2022, Aneeshkumar transitioned to Qualcomm later that same year, progressing to a senior role by November 2024. Currently, at Astera Labs since March 2025, Aneeshkumar specializes in formal verification of PCIe switch schedulers, emphasizing arbitration, fairness, and QoS guarantees, while also focusing on property-based verification techniques. Educational qualifications include a Bachelor of Technology in Electrical and Electronics Engineering from Lovely Professional University and training in RTL design and verification at Maven Silicon.
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