Avinash John

Avinash John is a Senior Principal Engineer at Astera Labs, with over 10 years of experience in the validation of complex IPs. They currently lead the PCIe 5.0 and CXL Subsystem Prototyping and Validation in Silicon. Avinash has a background in electrical validation and debug for high-speed SerDes protocols and has defined hardware architecture for FPGA-based prototyping platforms. Previously, Avinash held various engineering roles at Cadence Design Systems, including Principal Design Engineer and Director of Systems Validation, and began their career as a Silicon Validation Engineer at Cosmic Circuits after earning a Bachelor's degree in Electrical, Electronics, and Communications Engineering from Model Engineering College, Cochin. They are also pursuing further education at Vidyodaya.