Duc Phan is a Principal Design Verification Engineer at Astera Labs, where they build and manage the Design Verification Team, focusing on advanced verification for high-speed communications. With over 11 years of extensive experience in design verification, Duc has worked in various engineering roles, including at DreamBig Semiconductor Inc., FPT Software, and FPT Japan Holdings. Duc's expertise encompasses MCU system control, UVM, SystemVerilog, and various EDA tools. Duc obtained a Bachelor's degree in Electrical, Electronics and Communications Engineering from Ho Chi Minh City University of Technology and Education in 2014.
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