Mohd Atif

Mohd Atif is a Tech Lead Design Verification Engineer at Astera Labs, bringing a wealth of experience from EdgeQ Inc. and a background in electronics engineering with a Master's degree from MNNIT Allahabad. Atif has a robust understanding of VLSI and semiconductor design, specializing in PCIe, Ethernet, and SoC verification using System Verilog and UVM. They have demonstrated capabilities in developing verification environments, ensuring protocol compliance, and optimizing testing processes. Through previous roles as a teaching assistant and intern, Atif honed critical skills in digital design and verification, further complemented by their strong problem-solving and teamwork abilities.