Vincent Fei

Vincent Fei is an ASIC Verification Engineer with 15 years of extensive experience in high-speed, low-power ASIC logic design and design verification. Vincent has expertise in micro-architecture definition, RTL implementation, logic synthesis, and various verification methodologies such as VMM and UVM based on SystemVerilog. They have worked at notable companies, including Marvell Semiconductor, AMD, and Intel Corporation, contributing to projects involving memory controllers, Ethernet switches, and chiplet connections. Vincent holds a Bachelor’s and Master’s degree in Electrical Automation and Electronics Engineering from Shanghai University. Currently, they work as a Principal Design Verification Engineer at Astera Labs.