William Wen is a Technical Lead at Astera Labs since April 2022, having previously held the position of MTS Silicon Design Engineer at AMD from May 2012 to May 2022, focusing on Display IP. Prior experience includes roles as Senior Engineer and Eng 2 at AMD, as well as serving as a Design Verification Engineer Intern from May 2010 to August 2011. William Wen holds a Bachelor of Science degree in Electrical Engineering from the University of Toronto, earned between 2007 and 2012.
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