Jiangping FU

Jiangping Fu is a Senior Lead Engineer specializing in ASIC design at ASTRI in Hong Kong. With a Master's degree in Computer Architecture from Northwestern Polytechnical University, they have extensive experience in AI system design, H.264/HEVC encoding, and ASIC/FPGA design. Previously, they worked as an ASIC Design Engineer at ZhuHai JieLi Technology Co., Ltd., contributing to the design and verification of video and audio chips, and as an IC Design Engineer at ZTE Corporation, where they focused on multimedia chip design. Jiangping has also held the position of FPGA Engineer at ASTRI, implementing algorithms and managing FPGA designs.