Rakesh Hegde

Rakesh Hegde is a Technical Lead for Software at Atonarp. Prior to their current position, they worked as an R&D Engineer - RTL Design for Tejas Networks from August 2013 to May 2014. While at Tejas Networks, Hegde was part of the Ethernet Product Group and FPGA team where they designed and successfully implemented the Channelized Circuit Emulation over Packet (CEP) technology. Additionally, Hegde modified existing RTL functional blocks using Verilog, integrated all functional RTL modules into a top-level system, performed timing analysis and sorted timing errors, and completed error debugging and troubleshooting. Rakesh also documented design specifications and test procedures, and successfully tested the target at different ppm levels and for various errors.

Rakesh Hegde has a Master of Science in Technology (M.Sc. Tech) in VLSI Design from Manipal Institute of Technology and a Bachelor of Engineering (B.E.) in Electronics & Telecommunication from Goa College of Engineering.

Their manager is Karthikeyan Madathil, VP, Software & Algorithms. They work with Mahadeva HN - Senior Software Engineer, Srikanth A V - Senior Software Engineer, and Ganesh Shanbhag - Embedded Software Engineer. A direct report to Rakesh Hegde is and Siddharth Singh - Technical Staff Member.