Harshitha V is currently a Lead Engineer at Auradine, where they have been focusing on digital standard cells since September 2013. They previously held positions as a Lead Layout Engineer and Senior Layout Engineer at Qualcomm from 2023 to 2025, specializing in standard cell layout development and automation. Prior to that, Harshitha worked as a Senior Layout Design Engineer at Intel Corporation from 2016 to 2020 and began their career as a Layout Design Engineer at Sankalp Semiconductor Pvt Ltd from 2013 to 2016. Harshitha holds a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Visvesvaraya Technological University, earned in 2013.
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