Michael Kerr

Michael Kerr is a Circuit Design Engineer at BAE Systems, Inc. since February 2020, specializing in VHDL/FPGA circuit design. Prior to this role, Michael served as a Principal Member of Technical Staff at GLOBALFOUNDRIES, leading a global design team in advancing ASIC AreaArray GPIO and Specialty IO technologies using 7nm FinFET processes. Michael's extensive experience at IBM included positions as a Senior Engineer focused on ASIC IO Design and an Advisory Engineer in Chip Carrier Design, where responsibilities encompassed technical leadership, documentation, circuit simulation, and signal integrity analysis. Early in Michael's career, a role as a Software Engineer at Standard Pennant Company included developing an inventory and order tracking system. Michael holds a Bachelor of Science and a Master of Science in Electrical and Electronics Engineering from Penn State University and Binghamton University, respectively.