Sergey Shatalov

Lead Soc ASIC Physical Design Engineer at Baikal Electronics

Sergey Shatalov has a work experience in the field of electronics spanning over several years. Sergey began their career at Freescale Semiconductor in 2007, where they worked as a Back-end engineer until 2009. Sergey then transitioned to the role of Characterization and view validation engineer from 2010 to 2012. In 2012, they joined Milandr as a Lead SoC Back-end engineer. Currently, they are serving as a Lead Soc ASIC physical design engineer at Baikal Electronics, starting from 2022.

Sergey Shatalov holds a Master's degree in Physics, Nano electronics from the Moscow Institute of Electronic Technology (Technical University), which they obtained from 2003 to 2009. Sergey also has a secondary-level education from school 1151, completed from 1993 to 2003. In terms of additional certifications, Sergey has obtained certifications in Allegro Sigrity Package Assessment and Model Extraction, Low Power Implementation Front End and Back End, and Cadence QRC User Transistor-level Extraction. The years of completion for these certifications are not provided.

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Timeline

  • Lead Soc ASIC Physical Design Engineer

    April, 2022 - present