Abhijith Aithal is an experienced FPGA Engineer with a background in digital design engineering. Abhijith has worked on RTL development for ASICs and FPGAs using Verilog and VHDL. Abhijith also has experience in formal verification, synthesis of RTL circuits, and hardware-near software development for HW-validation. In addition, Abhijith has completed a Master's degree in Electrical, Electronics, and Communications Engineering.
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