J Antineo is a dedicated Lead Design Verification Engineer at BITSILICA and a SBIO Design Verification Engineer at AMD. They previously worked as an IC Design Engineer at Synkom Co., Ltd. from 2018 to 2022, and as a Design Verification Engineer at Canon Information Technology (Philippines) between 2014 and 2017. Earlier in their career, J completed an On The Job Trainee position at Chiyoda Corporation in 2013 and started their professional journey as an Associate Design Verification Engineer at Verification Technology, Inc. in 2018.
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