Vivek G is an experienced design verification engineer currently at BITSILICA since April 2025, following a role as a verification engineer at SmartDV Technologies from June 2023 to January 2025. Earlier experience includes a position in VLSI design foundation at Tech Mahindra Cerium Pvt Ltd from January 2023 to April 2023. Vivek G specializes in verifying and debugging complex digital designs using industry-standard methodologies and has expertise in protocols such as Ethernet, RoCE, and Ethernet 10Base-T1S VIPs, contributing to the development of verification IPs for major clients. Educational background includes a Bachelor of Technology in Electronics and Communications Engineering from Sri Venkateswara College of Engineering, Tirupati, with an impressive academic record of 85%.
This person is not in the org chart
This person is not in any teams
This person is not in any offices