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BitSilica
Unverified
RTL Design Engineering
9 people · 0 jobs
This department focuses on the design and development of RTL (Register Transfer Level) architectures for ASIC and FPGA implementations.
Jagadeesh Yarramshetty
RTL Design Trainee Engineer
Jhansi Madem
RTL Design Engineer
Katla Kamalakar
Senior engineer rtl design
Mounika N.
RANJEET KISHORE BAL
Shinnu M S
Vasudevan Devaraj
Senior Lead RTL Design Engineer
Viswanadh Yellumraju
RTL design engineer
YANAMADALA KRISHNA SAI
ASIC/RTL Design Engineer
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