Ajin Thapa

Ajin Thapa is an R&D ASIC Engineer at Broadcom Inc., specializing in Bluetooth MAC ASIC design. With extensive experience in ASIC and FPGA design, Ajin has worked with SystemVerilog/Verilog for many years, focusing on synthesis, static timing analysis, and design validation. Previously, Ajin held positions at Hewlett Packard Singapore, ASML, and Agilent Technologies, contributing to various projects and interfacing with customers. Ajin earned a Bachelor of Engineering in Communication Engineering with honors from RMIT University.