AMARENDRA GONUPALLI

Amarendra Gonupalli is a Senior Physical Design and STA Engineer with extensive experience in ASIC Physical Design, having worked on various projects across multiple technology nodes from 3nm to 40nm. Currently employed at Broadcom, Amarendra has contributed to six successful tape-outs and has expertise in physical design processes, including floor planning, placement, and static timing analysis. Previously, Amarendra held senior engineering roles at Synapse Techno Design Innovations and Cerium Systems, showcasing a robust skill set in EDA tools and scripting. Amarendra holds a Bachelor of Engineering in Electronics and Communication Engineering from Geethanjali Institute of Science and Technology.