Avinash Patil

Avinash Patil is a Senior Staff Verification Engineer in IC Design at Broadcom Inc., where they have been contributing since 2017. Previously, they worked as a Design Verification Engineer at TI from 2008 to 2017, specializing in ASIC design verification and adept in programming languages such as Verilog and System Verilog. Avinash holds a Bachelor’s Degree in Electronics and Communications Engineering from PES University, earned in 2008.