Chirag Shah is a Principal Engineer at Broadcom, bringing around 15 years of extensive ASIC experience in design verification. Previously, Chirag held positions as a Staff Engineer at Qualcomm, where they focused on wireless Wi-Fi verification, and as a Design Verification Engineer at Apple. Earlier in their career, Chirag worked as a Lead Design Engineer at Cadence Design Systems, specializing in PCIe, SATA, and USB3.0 IP verification, as well as contributing to USB3.0 Verification IP development at Synopsys. Chirag earned a Bachelor of Engineering in Electronics and Communications Engineering from Delhi College of Engineering in 2008.
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