Deepak Aradhana is currently an Engineering Manager and Principal Engineer R&D at Broadcom Inc., specializing in Analog SerDes layout and verification. With experience spanning from project trainee to senior design engineer, Deepak has worked on advanced technology nodes including TSMC's 5nm and 7nm FinFET processes. Deepak holds an MSc in Microelectronics from Manipal University and a B.Tech in Electronics and Communications Engineering. Prior to their current role at Broadcom, Deepak contributed to design and engineering at Avago Technologies and LSI Corporation.
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