Dhiraj Taneja

Dhiraj Taneja is a Senior Principal Engineer at Broadcom, specializing in ASIC implementation, synthesis, timing closure, and formal verification. Dhiraj led implementation efforts across various chips and technology nodes, including 90nm to 28nm, and previously worked as an MTS at AMD in the Consumer Electronics-DTV business unit. Prior experience includes serving as a Design Engineer II at ST Microelectronics, where Dhiraj was part of the library team focused on developing front-end views for embedded memories. Dhiraj also hosts a course on Advanced Logic Synthesis on NPTEL and holds both a BE in Electronics and Instrumentation and an ME in Microelectronics from the Birla Institute of Technology and Science.