Dominique Chen

Dominique Chen is a Sr. Principal Engineer at Broadcom, where they have worked since 2013 focused on RTL design and Verilog modeling for mixed-signal IPs. Prior to this, Dominique was a Member of Technical Staff at AMD beginning in 2009. They also served as a Senior Logic Design Engineer at Faraday Technology Inc. from 2006 to 2009, specializing in SATA PHY IP design and RTL optimization. Dominique holds a Master of Science in Electrical and Electronics Engineering from Penn State University and a Bachelor of Science in Electronics Engineering from National Chiao Tung University.