Harshit Shah is an experienced hardware engineer currently employed at Broadcom Inc. since July 2021. Previously, Shah held the position of memory compiler designer at TSMC North America from October 2017 to July 2021 and served as a Sr. Staff Design Engineer at Broadcom Limited from March 2013 to October 2017. Additionally, Shah was a Senior Design Engineer at ARM from February 2008 to March 2013 and a Rotational Engineer at Freescale Semiconductor from July 2007 to January 2008. Shah's expertise encompasses memory design, including 40nm to 20nm SRAM and RF memory compiler IP, with a strong focus on marginality, PPA improvement, and optimization techniques concerning timing, power, leakage, and read/write assists circuits. Educational qualifications include a Master’s degree in Electrical Engineering from Arizona State University and a Bachelor’s degree in Electrical Engineering from the University of Pittsburgh.
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