Jeff Riley

Jeff Riley is a Senior Principal IC Design Engineer at Broadcom, where they have worked since 2007, focusing on 10 Gb Ethernet copper PHY ASIC and data encryption technologies. With eleven years of experience in ASIC/FPGA design, Jeff has demonstrated technical expertise in areas including data compression, Verilog and VHDL modeling, and various synthesis tools. Previously, they held positions as an ASIC Design Engineer at Mindspeed, Quantum, and Conexant, as well as an Associate Engineer at t2design. Jeff earned a Bachelor of Science in Electrical Engineering with a focus on Application Specific Integrated Circuits from the University of Colorado Denver.