Jiwei di

Jiwei Di is an accomplished R&D Hardware Engineer at Broadcom, with professional experience dating back to September 2019. Prior to Broadcom, Jiwei Di held the position of Senior RTL Design Engineer at TetraMem, specializing in I2C/I3C controller design, APB bus protocols, SoC integration, and embedded programming. Jiwei Di also worked as a Staff IC Design Engineer at MediaTek, focusing on memory RTL modeling, memory compilers, arithmetic units, ATPG and DFT, UVM, low power simulation, and scan insertion technologies. Earlier experience includes a brief role as a Technology Development Engineer at GlobalFoundries, where responsibilities included post-silicon testing and defects analysis. Jiwei Di holds a Master of Engineering in Electrical and Electronics Engineering from Nanyang Technological University Singapore and a Bachelor of Science in Engineering Physics/Applied Physics from Tunghai University.