Kapil Raykar is a Principal Engineer at Broadcom, specializing in functional verification and gate level validation of ARM-based SOCs. With a strong foundation built over previous roles as a Senior Design Engineer at Xilinx and AMCC, and as a Module Leader at Wipro Technologies, Kapil has extensive experience in automated test environments, code coverage analysis, and embedded system integration. Kapil continues to advance their knowledge through current studies in VLSI Design and E&TC at Bit Mapper Integration Technologies and Pune University.
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