Naresh Thanugula is a Senior Physical Design Engineer at Broadcom, bringing extensive experience from roles at STM and MosChip. They have successfully managed multiple low power block designs for AMD and contributed to full chip timing closure on significant projects. Naresh holds a Bachelor of Technology in Electrical and Electronics Engineering from CVR College of Engineering, completed in 2017. With hands-on experience spanning various TSMC technology nodes and proficiency in industry-standard tools, they have participated in six tapeouts as a Physical Design Engineer.
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