Parag Gajjar

Parag Gajjar is an experienced professional in design verification (DV) with a strong background in mixed signal SoCs, particularly for safety-compliant automotive and industrial applications. Currently serving as a DV Lead at Broadcom since December 2010, Parag has previously held leadership roles at Marvell Technology, Teradyne, eInfochips Inc., AMD, Nevis Networks, VasuTech Ltd., and DCM Technologies, contributing to various projects involving DV efforts for Ethernet PHY ASICs, multimedia SoCs, and ASIC design and verification. Parag's educational background includes a Master of Business Administration from the University of Illinois Urbana-Champaign, a certification in Embedded System Design from UC Irvine, and degrees in ASIC & FPGA Chip Design and Electrical and Electronics Engineering.