Parag Waradkar is an R&D Engineer, IC Design 5 at Broadcom Inc. with over 10 years of experience in Silicon Validation and Embedded Software development. Currently engaged in networking chip projects, Parag has predominantly focused on network switch storage buffers and performance validation within networking chassis systems. They have developed and updated framework code for scheduler block validation and possess experience in programming with C and TCL. Parag holds a Bachelor of Engineering in Electrical and Electronics Engineering from Shivaji University and a diploma in the same field from G.O.V.T Polytechnic.
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