Praveen Sr is a Principal Engineer at Broadcom, specializing in SerDes cores verification using System Verilog. They have over 15 years of experience in the semiconductor industry, including previous roles as a Project Engineer at Wipro Technologies and a Design Engineer at AMD. Praveen contributed to the development of constrained random verification environments for projects such as the 802.11n MAC system and DDR3 PHY. They obtained a Bachelor of Engineering in Electronics and Communication from PES Institute of Technology, Bangalore.
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